The present disclosure is related to a semiconductor device, more specifically, a semiconductor device including capacitors having high capacitance and method of fabricating the same.
A method of realizing a high-capacity capacitor for an analogue circuit and radio frequency (RF) device requiring high-speed operation is being developed. In case the lower electrode and upper electrode of a capacitor are made of doped polysilicon, however, oxidation occurs in the interface between the lower electrode and the dielectric layer, and in the interface between the dielectric layer and the upper electrode, to form a natural oxide layer. This causes a decrease of capacitance.
In an attempted solution to the above problem, a metal-insulator-metal (MIM) capacitor is introduced. An MIM capacitor has only a small, specific resistance and has no parasitic capacitance resulting from inner depletion. Therefore, the MIM capacitor is typically used in high-performance semiconductor devices. In addition, in an MIM capacitor it is relatively easy to control the capacitance, compared to a poly-insulator-poly (PIP) capacitor, and an MIM capacitor causes less difference in capacitance when varied according to frequency. Therefore, an MIM capacitor is widely used in analog-to-digital converters (ADC), high-frequency devices, switching capacitor filters, and CMOS image sensors, for example.
FIG. 1A illustrates a cross-sectional view showing a portion of a conventional MIM capacitor, and FIG. 1B illustrates a circuit diagram of the capacitor of FIG. 1A.
Referring to FIG. 1A and FIG. 1B, a lower electrode 30 and an upper electrode 40 are disposed on a semiconductor substrate 10 having a bottom interconnection 26. A dielectric 38 is interposed between the lower electrode 30 and the upper electrode 40. A first insulation layer 28 is disposed between the lower electrode 30 and the semiconductor substrate 10, and a second insulation layer 48 is disposed on the first insulation layer 28. First, second and third top interconnections 52, 54 and 56 are disposed in the second insulation layer 48. The first top interconnection 52 is electrically connected to the upper electrode 40 through a first contact 53, and the second top interconnection 54 is electrically connected to the lower electrode 30 through a second contact 55. The third top interconnection 56 is electrically connected to the bottom interconnection 26 through a third contact 57. As shown in FIG. 1B, the first top interconnection 52 is also electrically connected to a first external terminal A, and the second top interconnection 54 is electrically connected to a second external terminal B. The upper electrode 40 and the lower electrode 30 constitute a capacitor C1 shown in FIG. 1B.
A capacitance above a predetermined level is required for stable operation of a semiconductor device. However much area the capacitor occupies decreases due to a continuous scaling down of the semiconductor device, thereby to cause a corresponding decrease of capacitance. Accordingly, a capacitor having a high capacitance in a limited area is demanded.